1. Technical Field of the Invention
The present invention relates to a semiconductor device and method for manufacturing the same. In particular, the present invention relates to a construction for a resistance component and method for manufacturing the same.
2. Background Art
As in the past, the refinement and high densification of semiconductor components are energetically being advanced. Currently, developmental testing is being performed on ultra integrated semiconductor devices such as memory devices, logic devices and the like, which are designed at a dimensional standard of 0.15.about.0.25 micrometers. Accompanying this high integration of semiconductor devices has been a particular demand for decreasing the diffusion layer width dimensions, as well as reducing the thickness of materials comprising the semiconductor components.
In this manner, conjugation reduction of the diffusion layer results in an increase in the parasitic resistance of the MOS transistor, and a decrease in the driving capabilities of this MOS transistor. Hence, with regard to the refinement of a semiconductor device, a technology for forming a silicide layer of a high melting point metal onto the surface of either the diffusion layer or gate electrode becomes important. In particular, silicide technology or Salicide technology (self-aligned silicide technology) using titanium as the high melting point metal is indispensable to a refined MOS transistor.
On the other hand, in a semiconductor device, in order to construct a logical circuit or input protection circuit, it is essential to form a resistance component by means of a diffusion layer. However, when the surface of the diffusion layer is silicidized (reacted to form a silicide) or Salicidized (reacted under Salicide technology), the resistance of the diffusion layer decreases thereby rendering formation of a resistance component impossible.
Hence, in a semiconductor device wherein a silicide layer is formed onto the surface of a diffusion layer as mentioned above, the silicide layer on top of the diffusion layer forming the resistance component is selectively removed.
In the following, a conventional example relating the aforementioned case will be explained based on FIG. 7. FIG. 7A is a diagram showing a plan view of a resistance component.
FIG. 7B is a diagram showing a cross-sectional view of a resistance component along the line A'-B' of FIG. 7A.
As shown in FIG. 7A, an impurity diffusion Layer 103 is provided which is enclosed by a component separating-insulating layer 102. Here, a silicide layer is not formed onto impurity diffusion layer 103. Instead, silicide layers 104 are formed in the areas at both ends of impurity diffusion layer 103. Furthermore, contact apertures 105 are formed in a predetermined area of silicide layer 104, by means of which silicide layer 104 communicates with electrode 106.
In the following, the cross-sectional structure of this type of resistance component will be explained with reference to FIG. 7B. As shown in FIG. 7B, a component separating-insulating layer 102 is selectively formed in a predetermined region on the surface of silicon base 101. In addition, an impurity diffusion layer 103 is formed in a region on the surface of silicon base 101 wherein component separating-insulating layer 102 is not formed. As shown in FIG. 7B, silicide layers 104 are formed only at the terminal areas at both ends of the aforementioned impurity diffusion layer 103. Furthermore, an interlayer insulating Layer 107 is formed covering the entire surface thereof with contact apertures 105 provided in the areas in which interlayer insulating layer 107 overlies silicide layers 104. Additionally, an electrode 106 is provided which electrically communicates with silicide layer 104 via contact apertures 105.
Here, the electrical resistance of the silicide layer 104 areas is extremely low. As a result, the resistance of the resistance component possessing the aforementioned structure is determined by means of the resistance of the impurity diffusion layer in the area which does not contain a silicide layer on the surface thereof. Furthermore, the impurity diffusion layer area which does not contain a silicide layer on the surface thereof is formed by means a process in which a metallic layer for use in silicide formation is adhered to the entire surface of the impurity diffusion layer, followed by selective removal of the metallic layer from area(s) wherein a silicide layer is not formed.
In the case of this type of conventional technology, formation of an area on the surface of the impurity diffusion layer which does not contain a silicide layer requires a process for selectively removing the metallic layer which is to be used in silicidation (formation of silicide) from area(s) wherein the aforementioned silicide layer is not formed. As a result, it is necessary to add at least one photolithography process and/or dry-etching process. This aspect, however, serves as the main impediment to shortening the manufacturing process for manufacturing the aforementioned semiconductor device.
In addition, in the formation of the impurity diffusion layer according to the aforementioned conventional example, the introduction of impurities into the impurity diffusion layer is conducted at the same time as the formation of the source-drain region of the MOS transistor. As a result, the impurity concentration of the impurity diffusion layer is generally high. Thus, an extended formation of a impurity diffusion layer is required in order to form a resistance component possessing a high resistance (i.e., when a resistance component possessing a high resistance is necessary). This aspect hinders the high integration or high densification of a semiconductor device.
Alternatively, in the case of the aforementioned conventional example, it is possible to reduce the impurity concentration within the impurity diffusion layer when forming the source-drain diffusion region of the MOS transistor by means of an Lightly Doped Drain (LDD) structure. However, this in turn requires that a mask for preventing the introduction of a high concentration of impurities be formed once into the impurity diffusion layer. As a result, the aforementioned case requires the addition of another round of the photolithography step.